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1 ltc1064 low noise, fast, quad universal filter building block n four filters in a 0.3-inch wide package n one half the noise of the ltc1059/ltc1060/ ltc1061 devices n maximum center frequency: 140khz n maximum clock frequency: 7mhz n clock-to-center frequency ratio of 50:1 and 100:1 simultaneously available n power supplies: 2.375v to 8v n low offsets n low harmonic distortion n customized version with internal resistors available the ltc ? 1064 consists of four high speed, low noise switched-capacitor filter building blocks. each filter build- ing block, together with an external clock and three to five resistors can provide various 2nd order functions like lowpass, highpass, bandpass and notch. the center fre- quency of each 2nd order function can be tuned with an external clock, or a clock and resistor ratio. for q 5, the center frequency range is from 0.1hz to 100khz. for q 3, the center frequency range can be extended to 140khz. up to 8th order filters can be realized by cascading all four 2nd order sections. any classical filter realization (such as butterworth, cauer, bessel and chebyshev) can be formed. a customized monolithic version of the ltc1064 includ- ing internal thin film resistors can be obtained for high volume applications. consult ltc marketing for details. the ltc1064 is manufactured using linear technologys enhanced ltcmos tm silicon gate process. descriptio n u features gain vs frequency typical applicatio n u clock-tunable 8th order cauer lowpass filter with f cutoff up to 100khz inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 10k 18.25k 10.7k 10k 12.1k 17.4k r h2 102k 13k 66.5k r l2 26.7k 41.2k 12.7k 14k 121k 10k 22.1k v in 8v (from r h2 , r l2 ) 5mhz 0.1 m f 0.1 m f ?v pin 12 v out 1064 ta01 8v 10k 49.9k 11.5k for f clk = 5mhz, add c1 = 10pf between pins 4, 1 c2 = 10pf between pins 21, 24 c3 = 27pf between pins 9, 12 wideband noise @ 140 m v rms , ltc and lt are registered trademarks of linear technology corporation. ltcmos is a trademark of linear technology corporation. input frequency (hz) 1k gain (db) 10k 100k 1m 1064 ta02 0 15 30 45 60 75 90 105 120 135 f clk = 5mhz ripple = 0.1db f clk = 1mhz ripple = 0.05db n anti-aliasing filters n wide frequency range tracking filters n spectral analysis n loop filters applicatio n s u
2 ltc1064 absolute m axi m u m ratings w ww u electrical characteristics package/order i n for m atio n w u u t jmax = 150 c, q ja = 100 c/ w (j) t jmax = 110 c, q ja = 65 c/ w (n) LTC1064ACJ ltc1064cj ltc1064amj ltc1064mj ltc1064acn ltc1064cn ltc1064cs order part number order part number t jmax = 100 c, q ja = 85 c/ w consult factory for industrial grade parts. parameter conditions min typ max units operating supply voltage range 2.375 8v voltage swings v s = 5v, r l = 5k 3.2 3.6 v l 3.1 v output short-circuit current (source/sink) v s = 5v 3 ma dc open-loop gain v s = 5v, r l = 5k 80 db gbw product v s = 5v 7 mhz slew rate v s = 5v 10 v/ m s (internal op amps) t a = 25 c, unless otherwise specified. total supply voltage (v + to v C ) ............................. 16v power dissipation ............................................. 500mw operating temperature range ltc1064ac/ltc1064c .................... C 40 c to 85 c ltc1064am/ltc1064m ................ C 55 c to 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c 1 2 3 4 5 6 7 8 9 10 11 12 top view j package 24-lead ceramic dip 24 23 22 21 20 19 18 17 16 15 14 13 inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d n package 24-lead plastic dip sw package 24-lead plastic so 1 2 3 4 5 6 7 8 9 10 11 12 top view 24 23 22 21 20 19 18 17 16 15 14 13 inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d
3 ltc1064 electrical characteristics (complete filter) v s = 5v, t a = 25 c, ttl clock input level, unless otherwise specified. the l denotes specifications which apply over the full operating temperature range. parameter conditions min typ max units center frequency range, f o v s = 8v, q 3 0.1 to 140 khz input frequency range 0 to 1 mhz clock-to-center frequency ltc1064 f clk = 1mhz, f o = 20khz, pin 17 high 50 0.3 % ratio, f clk /f o ltc1064a (note 1) sides a, b, c: mode 1, l 50 0.8 % r1 = r3 = 5k, r2 = 5k, q = 10, sides d: mode 3, r1 = r3 = 50k l 50 0.9 % r2 = r4 = 5k ltc1064 same as above, pin 17 low, f clk = 1mhz 100 0.3 % ltc1064a (note 1) f o = 10khz sides a, b, c l 100 0.8 % side d l 100 0.9 clock-to-center frequency ltc1064 f clk = 1mhz 0.4 % ratio, side-to-side matching ltc1064a (note 1) l 1% clock-to-center frequency ltc1064 f clk = 4mhz, f o = 80khz, pin 17 high 50 0.6 % ratio, f clk /f o (note 2) ltc1064a (note 1) sides a, b, c: mode 1, v s = 7.5v 50 1.3 % r1 = r3 = 50k, r2 = 5k, q = 5 side d: mode 3, r1 = r3 = 50k r2 = r4 = 5k, f clk = 4mhz ltc1064 same as above, pin 17 low 100 0.6 % ltc1064 a (note 1) f clk = 4mhz, f o = 40khz 100 1.3 % q accuracy sides a, b, c: mode 1, q = 10 l 26 % side d: mode 3, f clk = 1mhz l 38 % f o temperature coefficient mode 1, 50:1, f clk < 2mhz 1 ppm/ c q temperature coefficient mode 1, 100:1, f clk < 2mhz 5 ppm/ c mode 3, f clk < 2mhz 5 ppm/ c dc offset voltage v os1 (table 1) f clk = 1mhz, 50:1 or 100:1 l 215 mv v os2 (table 1) f clk = 1mhz, 50:1 or 100:1 l 345 mv v os3 (table 1) f clk = 1mhz, 50:1 or 100:1 l 345 mv clock feedthrough f clk < 1mhz 0.2 mv rms maximum clock frequency mode 1, q < 5, v s 3 5v 7 mhz power supply current 91223 ma l 26 ma note 1: contact ltc marketing. note 2: not tested, guaranteed by design. v osn v osbp v oslp mode pins 2, 11, 14, 23 pins 3, 10, 15, 22 pins 4, 9, 16, 21 1v os1 [(1/q) + 1 + ? ? h olp ? ? ] C v os3 /q v os3 v osn C v os2 1b v os1 [(1/q) + 1 + (r2/r1)] C v os3 /q v os3 ~(v osn C v os2 )[1 + (r5/r6)] 2v os1 [(1 + (r2/r1) + (r2/r3) + (r2/r4) C v os3 (r2/r3)] v os3 v osn C v os2 [r4/(r2 + r4)] + v os2 [r2/(r2 + r4)] 3v os2 v os3 v os1 [1 + (r4/r1) + (r4/r2) + (r4/r3)] C v os2 (r4/r2) C v os3 (r4/r3) table 1. output dc offsets, one 2nd order section
4 ltc1064 + + + + + + + 50/100 (17) clk (18) hpc/nc (23) bpc (22) lpc (21) hpb/nb (2) bpb (3) lpb (4) bpa (10) lpa (9) inv a (12) agnd (6) inv c (24) 1064 bd hpa/na (11) + s sa (8) + + + + inv d (13) inv b (1) hpd (14) s sb (5) s sc (20) + + bpd (15) + lpd (16) v + (7) v ? (19) by tying pin 17 to v + , all sections operate with (f clk /f o ) = 50:1. by tying pin 17 to v , all sections operate with (f clk /f o ) = 100:1. by tying pin 17 to agnd, sections b, c operate with (f clk /f o ) = 50:1 and sections a, d operate at 100:1. typical perfor m a n ce characteristics uw mode 1, (f clk /f o ) = 50:1 mode 1, (f clk /f o ) = 100:1 mode 2, (f clk /f o ) = 25:1 block diagra w center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g01 100 110 120 t a = 25 c q = 5 q = 10 v s = 2.5v v s = 5v v s = 7.5v v s = 5v v s = 2.5v t a = 25 c q = 5 or 10 v s = 7.5v center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g02 100 110 120 t a = 25 c q = 5 q = 10 v s = 2.5v v s = 5v v s = 7.5v v s = 2.5v t a = 25 c q = 5 or 10 v s = 7.5v v s = 5v center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g03 100 110 120 t a = 25 c q = 10 pin 17 at v + (r2/r4) = 3 v s = 2.5v c c = 15pf v s = 5v c c = 15pf v s = 2.5v v s = 5v
5 ltc1064 typical perfor m a n ce characteristics uw mode 2, (f clk /f o ) = 25:1 mode 2, (f clk /f o ) = 50:1 mode 3, (f clk /f o ) = 50:1 mode 3, (f clk /f o ) = 50:1 mode 3, (f clk /f o ) = 100:1 wideband noise vs q q 2 0 wideband noise ( m v/ rms ) 240 220 200 180 160 140 120 100 80 60 40 20 0 46 10 8 12141618 1064 g09 20 22 24 any output r3 = r1 one second order section mode 1 or 3 100:1 or 50:1 7.5v 5v 2.5v power supply current vs supply voltage center frequency (khz) 20 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 40 60 100 80 120140 160180 1064 g04 200 t a = 25 c v s = 7.5v pin 17 at v + (r2/r4) = 3 q = 5 c c = 22pf q = 5 q = 2 q = 2 c c = 39pf center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g05 100 110 120 v s = 7.5v v s = 7.5v v s = 5v v s = 2.5v t a = 25 c pin 17 at v ? (r2/r4) = 3 q = 5 q = 10 v s = 2.5v v s = 5v center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g06 100 110 120 v s = 7.5v v s = 7.5v v s = 5v v s = 2.5v t a = 25 c c c = 5pf r2 = r4 q = 5 q = 10 v s = 2.5v v s = 5v center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g07 100 110 120 t a = 25 c c c = 15pf r2 = r4 v s = 7.5v q = 2 q = 1 v s = 5v v s = 2.5v v s = 7.5v center frequency (khz) 10 0 q error (%) center frequency error (%) 20 15 10 5 0 ? 1.5 1.0 0.5 0 20 30 50 40 60 70 80 90 1064 g08 100 110 120 v s = 7.5v v s = 7.5v v s = 2.5v t a = 25 c c c = 5pf r2 = r4 q = 10 v s = 2.5v v s = 5v v s = 5v power supply voltage (v + ?v ) 2 0 power supply current (ma) 48 44 40 36 32 28 24 20 16 12 8 4 0 46 10 8 12141618 1064 g10 20 22 24 ?5 c 25 c 125 c harmonic distortion, 8th order lp butterworth, f c = 20khz, thd = 0.015% for 3v rms input 1064 g11
6 ltc1064 pi n fu n ctio n s uuu agnd (pin 6): analog ground. when the ltc1064 oper- ates with dual supplies, pin 6 should be tied to system ground. when the ltc1064 operates with a single positive supply, the analog ground pin should be tied to 1/2 supply and it should be bypassed with a 1 m f solid tantalum in parallel with a 0.1 m f ceramic capacitor, figure 1. the positive input of all the internal op amps, as well as the common reference of all the internal switches, are inter- nally tied to the analog ground pin. because of this, a very clean ground is recommended. 50/100 (pin 17): by tying pin 17 to v + , all filter sections operate with a clock-to-center frequency ratio internally set at 50:1. when pin 17 is at mid-supplies, sections b and c operate with (f clk /f o ) = 50:1 and sections a and d operate at 100:1. when pin 17 is shorted to the negative supply pin, all filter sections operate with (f clk /f o ) = 100:1. v + , v C (pins 7, 19): power supplies. they should be bypassed with a 0.1 m f ceramic capacitor. low noise, nonswitching power supplies are recommended. the de- vice operates with a single 5v supply and with dual supplies. the absolute maximum operating power supply voltage is 8v. clk (pin 18): clock. for 5v supplies the logic threshold level is 1.4v. for 8v and 0v to 5v supplies the logic threshold levels are 2.2v and 3v respectively. the logic threshold levels vary 100mv over the full military tem- perature range. the recommended duty cycle of the input clock is 50%, although for clock frequencies below 500khz, the clock on time can be as low as 200ns. the maximum clock frequency for 5v supplies is 4mhz. for 7v supplies and above, the maximum clock frequency is 7mhz. figure 1. single supply operation 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 v clk 50/100 agnd v + analog ground plane note: pins 5, 8, 20, if not used, should be connected to pin 6 clock input v + = 15v, trip voltage = 7v v + = 10v, trip voltage = 6.4v v + = 5v, trip voltage = 3v to digital ground v + ltc1064 0.1 m f 5k 1064 f01 5k 1 m f + v+/2
7 ltc1064 applicatio n s i n for m atio n wu u u figure 2. example ground plane breadboard technique for ltc1064 analog considerations grounding and bypassing the ltc1064 should be used with separated analog and digital ground planes and single point grounding techniques. pin 6 (agnd) should be tied directly to the analog ground plane. pin 7 (v + ) should be bypassed to the ground plane with a 0.1 m f ceramic capacitor with leads as short as possible. pin 19 (v C ) should be bypassed with a 0.1 m f ceramic capacitor. for single supply applications, v C can be tied to the analog ground plane. for good noise performance, v + and v C must be free of noise and ripple. all analog inputs should be referenced directly to the single point ground. the clock inputs should be shielded from and/or routed away from the analog circuitry and a separate digital ground plane used. figure 2 shows an example of an ideal ground plane design for a two-sided board. of course this much ground plane will not always be possible, but users should strive to get as close to this as possible. protoboards are not recommended. buffering the filter output when driving coaxial cables and 1 scope probes, the filter output should be buffered. this is important espe- cially when high qs are used to design a specific filter. inadequate buffering may cause errors in noise, distor- tion, q and gain measurements . when 10 probes are used, buffering is usually not required. an inverting buffer is recommended especially when thd tests are per- formed. as shown in figure 3, the buffer should be adequately bypassed to minimize clock feedthrough. analog ground plane note: connect analog and digital ground planes at a single point at the board edge for best high frequency response place resistors parallel to double- sided copper clad board and lay flat (4 resistors shown here typical) ltc1064 0.1 m f ceramic pin 1 ident 1064 f02 5k 7.5v 7.5v 0.1 m f ceramic (single point ground) clock v in 1 2 3 4 5 6 7 8 9 10 11 12 digital ground plane 24 23 22 21 20 19 18 17 16 15 14 13
8 ltc1064 applicatio n s i n for m atio n wu u u offset nulling lowpass filters may have too much dc offset for some users. a servo circuit may be used to actively null the offsets of the ltc1064 or any ltc switched-capacitor filter. the circuit shown in figure 4 will null offsets to better than 300 m v. this circuit takes seconds to settle because of the integrator pole frequency. noise all the noise performance mentioned excludes the clock feedthrough. noise measurements will degrade if the already described grounding bypassing and buffering techniques are not practiced. the graph wideband noise vs q in the typical performance characteristics section is a very good representation of the noise performance of this device. figure 3. buffering the output of a 4th order bandpass realization figure 4. servo amplifier primary modes mode 1 in mode 1, the ratio of the external clock frequency to the center frequency of each 2nd order section is internally fixed at 50:1 or 100:1. figure 5 illustrates mode 1 provid- ing 2nd order notch, lowpass and bandpass outputs. mode 1 can be used to make high order butterworth lowpass filters; it can also be used to make low q notches and for cascading 2nd order bandpass functions tuned at the same center frequency with unity gain. mode 1 is faster than mode 3. note that mode 1 can only be implemented with three of the four ltc1064 sections because section d has no externally available summing node. section d, however, can be internally connected in mode 1 upon special request. odes of operatio u w 7 19 r21 r11 r31 4 7 ltc1064 0.1 m f 1 m f 1064 f03 10k r32 r22 r12 0.1 m f v + trace for filter 0.1 m f v in + 10k lt 318 lt1007 lt1056 negative supply positive supply separate v + power supply trace for buffer + 1 m f 0.1 m f + + lp 1064 f05 + s agnd 1/4 ltc1064 ns r1 r2 v in r3 f o = ; f n = f o ; h olp = ? ; h obp = ? ; h on1 = ? ; q = f clk 100(50) r2 r1 r3 r1 r3 r2 r2 r1 bp figure 5. mode 1: 2nd order filter providing notch, bandpass and lowpass c2 0.1 m f c1 0.1 m f r1 1m r2 1m 1064 f04 to filter first summing node c1 = c2 = low leakage film (i.e. polypropylene) r1 = r2 = metal film 1% from filter output r3 100k + lt1012
9 ltc1064 mode 3 mode 3 is the second of the primary modes. in mode 3, the ratio of the external clock frequency to the center fre- quency of each 2nd order section can be adjusted above or below 50:1 or 100:1. side d of the ltc1064 can only be connected in mode 3. figure 6 illustrates mode 3, the classical state variable configuration, providing highpass, bandpass and lowpass 2nd order filter functions. mode 3 is slower than mode 1. mode 3 can be used to make high order all-pole bandpass, lowpass, highpass and notch filters. when the internal clock-to-center frequency ratio is set at 50:1, the design equations for q and bandpass gain are different from the 100:1 case . this was done to provide speed without penalizing the noise performance. + lp + s agnd hp s 1/4 ltc1064 bp r1 r2 v in r3 r4 1064 f06 c c 1064 f06 eq note: the 50:1 equations for mode 3 are different from the equations for mode 3 operations of the ltc1059, ltc1060 and ltc1061. start with f o , calculate r2/r4, set r4; from the q value, calculate r3: f o = ; q = ; h ohp = ? ; f clk 100 r2 r4 r3 r2 r2 r4 r2 r1 mode 3 (100:1): ? ? h obp = ? ; h olp = ? r3 r1 r4 r1 f o = ; q = ; f clk 50 r2 r4 mode 3 (50:1): ? r2 r3 r2 16r4 r2 r4 1.005 ? r3 = ; then calculate r1 to set the desired gain. + r2 1.005 q ? r2 r4 r2 16r4 r3 r1 h ohp = ? ; h obp = ? ; h olp = ? r2 r1 r3 16r4 1 r4 r1 secondary modes mode 1b mode 1b is derived from mode 1. in mode 1b, figure 7, two additional resistors r5 and r6 are added to alternate the amount of voltage fed back from the lowpass output into the input of the sa (or sb or sc) switched-capacitor summer. this allows the filters clock-to-center frequency ratio to be adjusted beyond 50:1 or 100:1. mode 1b maintains the speed advantages of mode 1. + lp + s agnd ns bp r1 r2 v in r3 1064 f07 r6 r5 1/4 ltc1064 1064 f07 eq f o = ; f n = f o; q = ; f clk 100(50) f clk 2 r3 r2 r2 r1 r6 r5 + r6 ? r6 r5 + r6 ? h on1 (f ? 0) = h on2 f ? = ? ; h olp = ? ; h obp = ? ; r5 ? ? r6 5k r3 r1 () r6 r5 + r6 r2 r1 mode 2 mode 2 is a combination of mode 1 and mode 3, as shown in figure 8. with mode 2, the clock-to-center frequency ratio f clk /f o is always less than 50:1 or 100:1. the advantage of mode 2 is that it provides less sensitivity to resistor tolerances than does mode 3. as in mode 1, mode 2 has a notch output which depends on the clock fre- quency and the notch frequency is therefore less than the center frequency f o . when the internal clock-to-center frequency ratio is set at 50:1, the design equations for q and bandpass gain are different from the 100:1 case . odes of operatio u w figure 6. mode 3: 2nd order filter providing highpass, bandpass and lowpass figure 7. mode 1b: 2nd order filter providing notch, bandpass and lowpass
10 ltc1064 odes of operatio u w + lp 1064 f08 + s agnd ns 1/4 ltc1064 r1 r2 v in r3 r4 bp figure 8. mode 2: 2nd order filter providing notch, bandpass and lowpass mode 3a this is an extension of mode 3 where the highpass and lowpass outputs are summed through two external resis- tors r h and r l to create a notch. this is shown in figure 9. mode 3a is more versatile than mode 2 because the notch frequency can be higher or lower than the center frequency of the 2nd order section. the external op amp of figure 9 is not always required. when cascading the sections of the ltc1064, the highpass and lowpass out- puts can be summed directly into the inverting input of the next section. the topology of mode 3a is useful for elliptic highpass and notch filters with clock-to-cutoff frequency ratios higher than 100:1. this is often required to extend the allowed input signal frequency range and to avoid premature aliasing. when the internal clock-to-center frequency ratio is set at 50:1, the design equations for q and bandpass gain are different from the 100:1 case . + lp + s agnd hp s 1/4 ltc1064 bp r1 r2 v in r3 r4 1064 f09 c c r l r h r g notch external op amp or input op amp of the ltc1064, side a, b, c, d + figure 9. mode 3a: 2nd order filter providing highpass, bandpass, lowpass and notch 1064 f08eq f o = 1 + ; f n = ; q = 1 + ; h olp = ? ; f clk 100 r2 r4 r3 r2 mode 2 (100:1): note: the 50:1 equations for mode 2 are different from the equations for mode 2 operation of the ltc1059, ltc1060 and ltc1061. start with f o , calculate r2/r4, set r4; from the q value, calculate r3: ? r2 r4 ? r2 r4 ? f o = 1 + ; f n = ; q = ; h olp = ? ; f clk 50 f clk 50 f clk 50 mode 2 (50:1): r2 r3 r2 16r4 r2 r4 1.005 1 + ? r3 r1 h obp = ? ; h on1 (f ? 0) = ? ; h on2 = f ? = r3 16r4 1 r2 r4 r3 = ; then calculate r1 to set the desired gain. 1 + + r2 1.005 q ? r2 16r4 r2 r1 r2 r4 1 + r2 r1 r2 r1 r2 r4 1 + r2 r1 r2 r4 1 + f clk 2 () f clk 2 () h obp = ? ; h on1 (f ? 0) = ? ; h on2 f ? = ? r3 r1 r2 r1 r2 r1 r2 r4 1 + 1064 f09eq f o = ; f n = ; h ohp = ; hobp = f clk 100 r2 r4 r h r l mode 3a (100:1): note: the 50:1 equations for mode 3a are different from the equations for mode 3a operation of the ltc1059, ltc1060 and ltc1061. start with f o , calculate r2/r4, set r4; from the q value, calculate r3: ? r2 r4 ? ? f clk 100 r2 r4 r3 = ; then calculate r1 to set the desired gain. + r2 1.005 q ? r2 16r4 r2 r1 r2 r3 r2 16r4 r2 r4 1.005 ? r3 r1 h obp = ? ; h olp (f = 0) = q = r3 16r4 1 r4 r1 ? ; r3 r1 ? ; r3 r2 r4 r1 f clk 2 () ()() ()() r h r l ? r2 r4 ? f o = 1 + ; f n = ; h ohp f ? = f clk 50 f clk 50 mode 3a (50:1): r2 r1 ? ; f clk 2 () () h olp = ? ; h on1 (f ? 0) = ; h on2 f ? = ; h on (f = f o ) = q h olp ? h ohp ; q = r4 r1 r2 r1 r g r l r g r l r g r h r g r h
11 ltc1064 wideband bandpass: ratio of high to low corner frequency equal to 2 inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r23 r33 r43 r24 r34 r44 r14 r13 r42 r32 r22 r12 r11 v in 5v to 8v f clk 7mhz c1 c2 0.1 m f 5v to 8v v out 1064 ta03 r41 r31 r21 0.1 m f resistor values: r11 = 16k r21 = 16k r31 = 7.32k r41 = 10k r12 = 10k r22 = 10k r32 = 22.6k r42 = 13.3k r13 = 23.2k r23 = 13.3k r33 = 21.5k r43 = 10k r14 = 6.8k r24 = 20k r34 = 15.4k r44 = 32.4k note: for f clk 3 3mhz, use c1 = c2 = 22pf amplitude response quad bandpass filter with center frequency equal to f o , 2f o , 3f o , and 4f o amplitude response inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r23 r33 r43 r13 r14 r44 r34 r24 20k r11 v in3 v in4 v in2 v in1 5v to 8v f clk 5v to 8v v out 1064 ta05 r12 r31 r21 17.4k 20k 20k 0.1 m f 10.5k resistor values: r11 = 249k r21 = 10k r31 = 249k r12 = 249k r22 = 10k r32 = 249k r13 = 499k r23 = 10k r33 = 174k r43 = 17.8k r14 = 453k r24 = 10k r34 = 249k r44 = 40.2k 0.1 m f + lt1056 typical applicatio n s u input frequency (hz) 10k gain (db) 15 0 15 30 45 60 75 90 105 100k 1m 1064 ta04 v s = 8v f clk = 7mhz f clk = 2mhz input frequency (khz) 0 gain (db) 5 0 ? 10 15 20 25 30 35 ?0 20 40 50 1064 ta06 10 30 f clk = 2mhz
12 ltc1064 typical applicatio n s u 8th order bandpass filter with 2 stopband notches amplitude response inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r42 r23 r33 r43 r13 r14 r12 r44 r34 r24 r11 v in 5v 0.1 m f ?v v out 1064 ta09 r41 r31 r21 0.1 m f resistor values: r11 = 88.7k r21 = 10k r31 = 35.7k r41 = 88.7k r12 = 10k r22 = 44.8k r32 = 33.2k r42 = 24.9k r13 = 15.8k r23 = 48.9k r33 = 63.5k r43 = 25.5k r14 = 15.8k r24 = 44.8k r34 = 16.5k r44 = 24.9k f clk = 3.5795mhz 16 c-message filter input frequency (khz) 0 gain (db) 2 4 5 1064 ta10 13 10 0 10 20 30 40 50 60 ?0 v s = 5v amplitude response inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r42 r h3 r11 v in to v + 5v to 8v 1.28mhz 5v to 8v v out 1064 ta07 r12 r41 r31 r21 0.1 m f r23 r33 r43 r h2 r44 r34 r24 r l2 resistor values: r11 = 46.95k r21 = 10k r31 = 38.25k r41 = 11.81k r12 = 93.93k r22 = 10k r32 = 81.5k r42 = 14.72k r l2 = 27.46k r h2 = 6.9k r23 = 16.3k r33 = 70.3k r43 = 10k r l3 = 17.9k r h3 = 69.7k r24 = 13.19k r34 = 39.42k r44 = 10.5k 0.1 m f r l3 note1: the v + , v pins should be bypassed with a 0.1 m f to 0.22 m f ceramic capacitor, right at the pins. note 2: the ratios of all (r2/r4) resistors should be matched to better than 0.25%. the remaining resistors should be better than 0.5% accurate. input frequency (khz) 15 gain (db) 10 0 10 20 30 40 50 60 ?0 10 20 40 100 1064 ta08 v s = 5v f clk = 1.28mhz pin 17 at v +
13 ltc1064 typical applicatio n s u inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r42 r21 r31 r41 r11 r l2 r44 r34 r24 7. 5v 0.1 m f ?.5v ?.5v v out v in 1064 ta13 r43 r33 r23 resistor values: r11 = 19.1k r21 = 10k r31 = 13.7k r41 = 15.4k r l1 = 14k r h1 = 30.9k r22 = 10k r32 = 23.7k r42 = 10.2k r l2 = 26.7k r h2 = 76.8k r23 = 11.3k r33 = 84.5k r43 = 10k r l3 = 10k r h3 = 60.2k r24 = 15.4k r34 = 15.2k r44 = 42.7k note: for t cutoff >15khz, add a 5pf capacitor across r41 and r43 f clk 2mhz r l1 r h1 r h2 r l3 r h3 0.1 m f inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r42 r23 r33 r43 r13 r14 r12 r44 r34 r24 r11 v in 5v to 8v 0.1 m f 5v to 8v 5v to 8v v out 1064 ta11 r41 r31 r21 0.1 m f resistor values: r11 = 100.86k r21 = 16.75k r31 = 23.6k r41 = 99.73k r12 = 25.72k r22 = 20.93k r32 = 45.2k r42 = 25.52k r13 = 16.61k r23 = 10.18k r33 = 68.15k r43 = 99.83k r14 = 13.84k r24 = 11.52k r34 = 17.72k r44 = 25.42k for f clk > 3mhz, add c2 = 10pf across r42 c3 = 10pf across r43 c4 = 10pf across r44 wideband noise = 170 m v rms f clk = 5mhz amplitude response frequency (khz) 0 0 15 30 45 60 75 90 105 30 50 1064 ta14 10 20 40 60 70 v out /v in (db) 8th order clock-sweepable lowpass elliptic antialiasing filter maintains, for 0.1hz f cutoff 20khz, a 0.1db max passband error and 72db min stopband attenuation at 1.5 f cutoff . total wideband noise = 150 m v rms , thd = 70db (0.03%) for v in = 3v rms , f clk /f cutoff = 100:1. this filter available as ltc1064-1 with internal thin film resistors. 8th order clock-sweepable lowpass elliptic antialiasing filter 8th order chebyshev lowpass filter with a passband ripple of 0.1db and cutoff frequency up to 100khz amplitude response input frequency (hz) 10k gain (db) 15 0 15 30 45 60 75 90 105 100k 1m 1064 ta12 v s = 8v f clk = 5mhz passband ripple = 0.1db
14 ltc1064 typical applicatio n s u inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r42 r23 r33 r43 r13 r44 r34 r24 8v 0.1 m f 8v ?v v out1 v out2 v in1 v in2 1064 ta15 r41 r31 r21 resistor values: r11 = 14.3k r21 = 13k r31 = 7.5k r41 = 10k r12 = 15.4k r22 = 15.4k r32 = 7.5k r42 = 10k r13 = 3.92k r23 = 20k r33 = 27.4k r43 = 40k r14 = 3.92k r24 = 20k r34 = 6.8k r44 = 10k wideband noise = 64 m v rms 7mhz clock r14 r11 r12 0.1 m f amplitude response dual 4th order bessel filter with 140khz cutoff frequency input frequency (hz) 10k gain (db) 15 0 15 30 45 60 75 90 105 100k 1m 1064 ta16 v s = 8v f clk = 7mhz amplitude response inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r21 r31 r41 r22 r32 r42 r12 r44 r34 r24 5v to 8v 0.1 m f to v + 5v to 8v to r13 v out v in1 from pin 20 1064 ta17 r43 r33 r23 resistor values: r11 = 34.8k r21 = 34.8k r31 = 14.3k r41 = 40.2k r12 = 10.5k r22 = 45.3k r32 = 22.1k r42 = 39.2k r13 = 12.7k r23 = 34.8k r33 = 24.3k r43 = 20k r14 = 20k r24 = 34.8k r34 = 13.3k r44 = 20k wideband noise = 70 m v rms f clk 7mhz r14 r13 r11 0.1 m f 8th order linear phase (bessel) filter with f clk = 65 f C3db 1 input frequency (hz) 10k gain (db) 15 0 15 30 45 60 75 90 105 100k 1m 1064 ta18 v s = 8v f clk = 4.5mhz f clk = 50% duty cycle f ?db = 70khz
15 ltc1064 typical applicatio n s u dual 5th order chebyshev lowpass filter with 50khz and 100khz cutoff frequencies information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r23 r33 r43 r24 r34 r44 r14 r42 r32 r22 8v 0.1 m f c2 1000pf 2pf c1 1000pf 22pf 39pf 4pf ?v v out2 f c = 100khz v out1 f c = 50khz v in2 v in1 1064 ta19 r41 r31 r21 resistor values: r11a = 4.32k r21 = 11.8k r31 = 29.4k r41 = 10k r11b = 27.4k r22 = 20k r32 = 21.5k r42 = 31.6k r12 = 10.5k r23 = 11.8k r33 = 29.4k r43 = 10k r13a = 3k r24 = 20k r34 = 21.6k r44 = 31.6k r13b = 29.4k r14 = 10.5k 5mhz t 2 l r12 r13b r13a r11b r11a 0.1 m f input frequency (hz) 10k 50k gain (db) 15 0 15 30 45 60 75 90 105 100k 1m 1064 ta20 passband ripple = 0.2db amplitude response related parts part number description comment ltc1061 triple universal filter building block three filter building blocks in a 20-pin package ltc1164 low power, quad universal filter building block low noise, low power pin-for-pin ltc1064 compatible ltc1264 high speed, quad universal building block up to 250khz center frequency inv b hpb/nb bpb lpb sb agnd v + sa lpa bpa hpa/na inv a 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 inv c hpc/nc bpc lpc sc v clk 50/100 lpd bpd hpd inv d ltc1064 r22 r32 r42 r23 r33 r14 r13 r44 r34 r24 8v 0.1 m f c3 c1 ?v f clk 5mhz v out v in1 1064 ta21 r12 r31 r21 resistor values: r11 = 50k r21 = 5k r31 = 50k r g = 68.1k r12 = 15.4k r22 = 10k r32 = 88.7k r42 = 48.7k r l4 = 10k (0.1%) r13 = 10k r23 = 10k r33 = 100k r h4 = 10k (0.1%) r14 = 9.09k r24 = 10k r34 = 63.4k r44 = 12.4k r l4 0.1% 0.1 m f r g r h4 0.1% r11 c2 + lt1056 c1 = c2 = c3 = 15pf the notch depth from 5khz to 30khz is 50db wideband noise = 300 m v rms clock-tunable, 30khz to 90khz 8th order notch filter providing notch depth in excess of 60db input frequency (khz) 10 gain (db) 10 0 10 20 30 40 50 60 70 80 90 100 110 20 30 40 50 1064 ta22 60 70 bw v s = 8v f clk = 4mhz amplitude response
16 ltc1064 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0895 2k rev a ? printed in usa ? linear technology corporation 1989 package descriptio n u dimension in inches (millimeters) unless otherwise noted. j24 0695 0.015 ?0.060 (0.381 ?1.524) 0.125 (3.175) min 0.014 ?0.026 (0.360 ?0.660) 0.100 0.010 (2.540 0.254) 0.200 (5.080) max 0.045 ?0.068 (1.143 ?1.727) 0.008 ?0.018 (0.203 ?0.457) 0.385 0.025 (9.779 0.635) 20 16 15 17 14 13 19 11 3 7 56 10 9 12 1 4 2 8 18 0.220 ?0.310 (5.588 ?7.874) 1.290 (32.77) max 21 22 23 24 0.025 (0.635) rad typ note: lead dimensions apply to solder dip/plate or tin plate leads. 0 ?15 0.300 bsc (0.762 bsc) 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) 0.005 (0.127) min j package 24-lead ceramic dip n package 24-lead plastic dip sw package 24-lead plastic so n24 0695 0.255 0.015* (6.477 0.381) 1.265* (32.131) 12 3 4 5 6 7 8910 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.015 (0.381) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) sw24 0695 note 1 0.598 ?0.614 (15.190 ?15.600) (note 2) 22 21 20 19 18 17 16 15 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 13 14 11 12 23 24 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299 (7.391 ?7.595) (note 2) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side

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